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| 1 2271f LTC2271 applications n low power instrumentation n software-de? ned radios n portable medical imaging n multi-channel data acquisition typical application description 16-bit, 20msps serial low noise dual adc the ltc ? 2271 is a 2-channel, simultaneous sampling 16-bit a/d converter designed for digitizing high frequency, wide dynamic range signals. it is perfect for demanding communications applications with ac performance that includes 84.1db snr and 99db spurious free dynamic range (sfdr). dc specs include 1lsb inl (typ), 0.2lsb dnl (typ) and no missing codes over temperature. the transition noise is 1.44lsb rms . to minimize the number of data lines the digital outputs are serial lvds. each channel outputs one bit, two bits or four bits at a time. the lvds drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. the enc + and enc C inputs may be driven differentially or single ended with a sine wave, pecl, lvds, ttl or cmos inputs. an internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. features n 2-channel simultaneous sampling adc n serial lvds outputs: 1, 2 or 4 bits per channel n 84.1db snr (46v rms input referred noise) n 99db sfdr n low power: 185mw total n 92mw per channel n single 1.8v supply n selectable input ranges: 1v p-p to 2.1v p-p n 200mhz full-power bandwidth s/h n shutdown and nap modes n serial spi port for con? guration n pin compatible with ltc2190: 16-bit, 25msps, 104mw n 52-lead (7mm 8mm) qfn package 16-bit adc core ch1 analog input ch2 analog input encode input s/h 16-bit adc core out1a out1b out1c out1d out2a out2b out2c out2d data clock out frame s/h data serializer pll ognd 2271 ta01 serialized lvds outputs gnd v dd ov dd 1.8v 1.8v l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. integral non-linearity (inl) output code 0 C2.0 C1.5 C1.0 inl error (lsb) C0.5 0.5 0.0 1.0 1.5 2.0 16384 32768 49152 65536 2271 ta02
LTC2271 2 2271f supply voltages v dd , ov dd ................................................ C0.3v to 2v analog input voltage a in +, a in C, par/ ser , sense (note 3) ....................................C0.3v to (v dd + 0.2v) digital input voltage enc + , enc C , cs , sdi, sck (note 4) ...... C0.3v to 3.9v sdo (note 4) ............................................ C0.3v to 3.9v digital output voltage ................ C0.3v to (ov dd + 0.3v) operating temperature range LTC2271c ................................................ 0c to 70c LTC2271i.............................................. C40c to 85c storage temperature range ................... C65c to 150c (notes 1, 2) 16 15 17 18 19 top view 53 gnd ukg package 52-lead (7mm s 8mm) plastic qfn 20 21 22 23 24 25 26 51 52 50 49 48 47 46 45 44 43 42 41 33 34 35 36 37 38 39 40 8 7 6 5 4 3 2 1 v cm1 gnd a in1 + a in1 C gnd refh refl refh refl par/ ser a in2 + a in2 C gnd v cm2 out1c + out1c C out1d + out1d C dco + dco C ov dd ognd fr + frC out2a + out2a C out2b + out2b C v dd v dd sense gnd v ref gnd sdo gnd out1a + out1a C out1b + out1b C v dd v dd enc + enc C cs sck sdi gnd out2d C out2d + out2c C out2c + 32 31 30 29 28 27 9 10 11 12 13 14 t jmax = 150c, ja = 29c/w exposed pad (pin 53) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LTC2271cukg#pbf LTC2271cukg#trpbf LTC2271ukg 52-lead (7mm 8mm) plastic qfn 0c to 70c LTC2271iukg#pbf LTC2271iukg#trpbf LTC2271ukg 52-lead (7mm 8mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ pin configuration absolute maximum ratings 3 2271f LTC2271 converter characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) parameter conditions min typ max units resolution (no missing codes) l 16 bits integral linearity error differential analog input (note 6) l C2.6 1 2.6 lsb differential linearity error differential analog input l C0.8 0.2 0.8 lsb offset error (note 7) l C7 1.3 7 mv gain error internal reference external reference l C1.6 1.2 C0.3 1 %fs %fs offset drift 10 v/c full-scale drift internal reference external reference 30 10 ppm/c ppm/c gain matching l C0.2 0.06 0.2 %fs offset matching l C10 1.5 10 mv transition noise 1.44 lsb rms analog input the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C) 1.7v < v dd < 1.9v l 1 to 2.1 v p-p v in(cm) analog input common mode (a in + + a in C)/2 differential analog input (note 8) l 0.65 v cm v cm + 200mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 20msps 32 a i in1 analog input leakage current (no encode) 0 < a in +, a in C < v dd l C1 1 a i in2 par/ ser input leakage current 0 < par/ ser < v dd l C1 1 a i in3 sense input leakage current 0.625v < sense < 1.3v l C2 2 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter single-ended encode differential encode 85 100 fs rms fs rms cmrr analog input common mode rejection ratio 80 db bwC3b full-power bandwidth figure 5 test circuit 200 mhz LTC2271 4 2271f dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions min typ max units snr signal-to-noise ratio 1.4mhz input 5mhz input 30mhz input 70mhz input l 82.3 84.1 84.1 83.8 82.7 dbfs dbfs dbfs dbfs sfdr spurious free dynamic range, 2nd harmonic 1.4mhz input 5mhz input 30mhz input 70mhz input l 88 99 98 98 90 dbfs dbfs dbfs dbfs spurious free dynamic range, 3rd harmonic 1.4mhz input 5mhz input 30mhz input 70mhz input l 88 99 98 98 96 dbfs dbfs dbfs dbfs spurious free dynamic range, 4th harmonic or higher 1.4mhz input 5mhz input 30mhz input 70mhz input l 93 110 110 105 100 dbfs dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 1.4mhz input 5mhz input 30mhz input 70mhz input l 81.8 83.9 83.9 83.7 82.0 dbfs dbfs dbfs dbfs crosstalk 10mhz input C110 dbc internal reference characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 l 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 l 1.230 1.250 1.270 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v digital inputs and outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd (note 8) l 0.2 3.6 v r in input resistance see figure 10 10 k c in input capacitance (note 8) 3.5 pf 5 2271f LTC2271 digital inputs and outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) symbol parameter conditions min typ max units single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd =1.8v l 1.2 v v il low level input voltage v dd =1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance see figure 11 30 k c in input capacitance (note 8) 3.5 pf digital inputs ( cs , sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd =1.8v l 1.3 v v il low level input voltage v dd =1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd =1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 3 pf digital data outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 power requirements the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 9) symbol parameter conditions min typ max units v dd analog supply voltage (note 10) l 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 v i vdd analog supply current sine wave input l 93.3 103 ma i ovdd digital supply current 1-lane mode, 1.75ma mode 1-lane mode, 3.5ma mode 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode 4-lane mode, 1.75ma mode 4-lane mode, 3.5ma mode l l l l l l 9.4 17.5 13.4 25.5 21.9 42 10.7 19.6 15.5 29 25 47 ma ma ma ma ma ma p diss power dissipation 1-lane mode, 1.75ma mode 1-lane mode, 3.5ma mode 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode 4-lane mode, 1.75ma mode 4-lane mode, 3.5ma mode l l l l l l 185 199 192 214 207 244 205 221 214 238 231 270 mw mw mw mw mw mw p sleep sleep mode power 1mw p nap nap mode power 50 mw p diffclk power increase with diffential encode mode enabled (no increase for sleep mode) 20 mw LTC2271 6 2271f timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 5) symbol parameter conditions min typ max units f s sampling frequency (note 10) l 5 20 mhz t encl enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 23.5 2 25 25 100 100 ns ns t ench enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 23.5 2 25 25 100 100 ns ns t ap sample-and-hold acquistion delay time 0ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 20mhz, 2-lane output mode, differential enc + /enc C = 2v p-p sine wave, input range = 2.1v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5lsb when the output code ? ickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = ov dd =1.8v, f sample = 20mhz, 2-lane output mode, enc + = single-ended 1.8v square wave, enc C = 0v, input range = 2.1v p-p with differential drive, unless otherwise noted. the supply current and power dissipation speci? cations are totals for the entire ic, not per channel. note 10: recommended operating conditions. symbol parameter conditions min typ max units digital data outputs (r term = 100 differential, c l = 2pf to gnd on each output) t ser serial data bit period 4-lane output mode 2-lane output mode 1-lane output mode 1/(4 ? f s ) 1/(8 ? f s ) 1/(16 ? f s ) sec t frame fr to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser sec t data data to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser sec t pd propagation delay (note 8) l 0.7n + 2 ? t ser 1.1n + 2 ? t ser 1.5n + 2 ? t ser sec t r output rise time data, dco, fr, 20% to 80% 0.17 ns t f output fall time data, dco, fr, 20% to 80% 0.17 ns dco cycle-cycle jitter t ser = 3.1ns 60 ps p-p pipeline latency 7 7 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs -to-sck setup time l 5ns t h sck-to- cs setup time l 5ns t ds sdi setup time l 5ns t dh sdi hold time l 5ns t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns 7 2271f LTC2271 timing diagrams 4-lane output mode analog input enc C n t ench t ap n+1 enc + dco C fr C out#a C d15 d13 d11 d9 d15 d13 d11 d9 d15 out#a + out#b C d14 d12 d10 d8 d14 d12 d10 d8 d14 out#b + out#c C d7 d5 d3 d1 d7 d5 d3 d1 d7 out#c + out#d C d6 d4 d2 d0 d6 d4 d2 d0 d6 out#d + sample nC7 sample nC6 sample nC5 2271 td01 dco + fr + t pd t encl t data t frame t ser t ser t ser 2-lane output mode d7 d5 d3 d1 d15 d13 d11 d9 d7 d5 d3 d1 d15 d13 d11 d6 d4 d2 d0 d14 d12 d10 d8 d6 d4 d2 d0 d14 d12 d10 analog input enc C n t ench t ap n+1 enc + dco C fr + out#a C out#a + out#b C out#b + dco + fr C t encl t ser t ser t data t frame t pd t ser sample nC5 2271 td02 sample nC6 sample nC7 out#c + , out#c C , out#d + , out#d C are disabled LTC2271 8 2271f timing diagrams 1-lane output mode d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 n+1 n d15 d14 d13 d12 analog input enc C t ench t ap enc + dco C fr + out#a C out#a + dco + fr C t encl t frame t data t ser t ser t pd t ser sample nC7 sample nC6 sample nC5 219210 td03 out#b + , out#b C , out#c + , out#c C , out#d + , out#d C are disabled a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/ w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 219210 td04 cs sck sdi r/ w sdo high impedance 9 2271f LTC2271 typical performance characteristics output code 0 C2.0 C1.5 C1.0 inl error (lsb) C0.5 0.5 0.0 1.0 1.5 2.0 16384 32768 49152 65536 2271 g01 output code C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0.0 0.4 0.2 0.6 0.8 1.0 2271 g02 0 16384 32768 49152 65536 frequency (mhz) C100 C140 C120 C60 C80 amplitude (dbfs) C40 0 C20 2271 g03 0 2 6 410 8 frequency (mhz) C100 C140 C120 C60 C80 amplitude (dbfs) C40 C20 0 2271 g04 024 6 810 frequency (mhz) C100 C140 C120 C60 C80 amplitude (dbfs) C40 C20 0 2271 g05 0 2 8 6 410 frequency (mhz) C100 C120 C140 C60 C80 amplitude (dbfs) C40 C20 0 2271 g06 0 2 6 410 8 frequency (mhz) 0 C100 C120 C140 C60 C80 amplitude (dbfs) C40 C20 0 2 6 410 8 2271 g07 frequency (mhz) 0 C120 C140 C80 C100 amplitude (dbfs) C60 0 C20 C40 246810 2271 g08 output code n-6 10000 5000 0 40000 35000 30000 25000 20000 15000 count n-5 n-4 n-3 n-2 n-1 n+6 n+5 n+4 n+3 n+2 n+1 n 2271 g09 integral non-linearity (inl) differential non-linearity (dnl) 64k point fft, f in = 1.4mhz, C1dbfs, 20msps 64k point fft, f in = 5.1mhz, C1dbfs, 20msps 64k point fft, f in = 10.1mhz, C1dbfs, 20msps 64k point fft, f in = 30.3mhz, C1dbfs, 20msps 64k point fft, f in = 70.3mhz, C1dbfs, 20msps 64k point 2-tone fft, f in = 14.8, 15.2mhz, C7dbfs, 20msps shorted input histogram LTC2271 10 2271f typical performance characteristics 0 20 40 60 80 100 120 140 input frequency (mhz) 83 82 81 80 79 85 84 snr (dbfs) 2271 g10 single-ended encode differential encode 0 20 40 60 80 100 120 140 input frequency (mhz) 95 90 85 80 75 70 105 100 2nd and 3rd harmonic (dbfs) 2271 g11 2nd 3rd input frequency (mhz) 0 85 80 75 70 90 2nd and 3rd harmonic (dbfs) 95 105 100 20 40 60 80 100 120 140 2271 g12 2nd 3rd input level (dbfs) C80 40 60 50 80 70 130 120 110 100 90 sfdr (dbc and dbfs) C70 C40 C50 C60 0 C10 C20 C30 2271 g13 dbfs dbc sense pin (v) 0.6 77 78 79 80 snr (dbfs) 81 82 85 84 83 0.8 0.7 1 1.2 1.1 0.9 1.3 2271 g16 80 85 sfdr (dbfs) 90 95 100 2271 g17 input common mode (v) 0.6 0.8 0.7 0.9 1.1 1 1.2 v dd 1.9v v dd 1.7v sample rate (msps) 0 80 90 snr, sfdr (dbfs) 100 110 10 51520 2271 g18 sfdr snr sfdr vs input level, f in = 5mhz, 20msps, 2.1v range snr vs input frequency, C1dbfs, 20msps, 2.1v range i vdd vs sample rate, 5mhz, C1dbfs sine wave input on each channel i ovdd vs sample rate, 5mhz, C1dbfs sine wave input on each channel snr, sfdr vs sample rate, f in = 5mhz, C1dbfs sfdr vs analog input common mode, f in = 9.7mhz, 20msps, 2.1v range snr vs sense, f in = 5mhz, C1dbfs 2nd, 3rd harmonic vs input frequency, C1dbfs, 20msps, 2.1v range 2nd, 3rd harmonic vs input frequency, C1dbfs, 20msps, 1.05v range sample rate (msps) 0 80 85 90 100 95 i vdd (ma) 5 101520 2271 g14 sample rate (msps) 0 10 5 15 20 45 40 35 30 25 i ovdd (ma) 51520 10 2271 g15 4 lane, 3.5ma 2 lane, 3.5ma 4 lane, 1.75ma 1 lane, 3.5ma 2 lane, 1.75ma 1 lane, 1.75ma 11 2271f LTC2271 pin functions v cm1 (pin 1): common mode bias output, nominally equal to v dd /2. v cm1 should be used to bias the common mode of the analog inputs of channel 1. bypass to ground with a 1f ceramic capacitor. gnd (pins 2, 5, 13, 22, 45, 47, 49, exposed pad pin 53): adc power ground. the exposed pad must be soldered to the pcb ground. a in1 + (pin 3): channel 1 positive differential analog input. a in1 C (pin 4): channel 1 negative differential analog input. refh (pins 6, 8): adc high reference. see the reference section in the applications information for recommended bypassing circuits for refh and refl. refl (pins 7, 9): adc low reference. see the reference section in the applications information for recommended bypassing circuits for refh and refl. par/ ser (pin 10): programming mode selection pin. connect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs , sck, sdi, sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. a in2 + (pin 11): channel 2 positive differential analog input. a in2 C (pin 12): channel 2 negative differential analog input. v cm2 (pin 14): common mode bias output, nominally equal to v dd /2. v cm2 should be used to bias the common mode of the analog inputs of channel 2. bypass to ground with a 1f ceramic capacitor. v dd (pins 15, 16, 51, 52): analog power supply, 1.7v to 1.9v. bypass to ground with 0.1f ceramic capacitors. adjacent pins can share a bypass capacitor. enc + (pin 17): encode input. conversion starts on the rising edge. enc C (pin 18): encode complement input. conversion starts on the falling edge. tie to gnd for single-ended encode mode. cs (pin 19): in serial programming mode, (par/ ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs along with sck selects 1-, 2- or 4-lane output mode (see table 3). cs can be driven with 1.8v to 3.3v logic. sck (pin 20): in serial programming mode, (par/ ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck along with cs selects 1-, 2- or 4-lane output mode (see table 3). sck can be driven with 1.8v to 3.3v logic. sdi (pin 21): in serial programming mode, (par/ ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming pode (par/ ser = v dd ), sdi can be used to power down the part. sdi can be driven with 1.8v to 3.3v logic. ognd (pin 33): output driver ground. this pin must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 34): output driver supply. bypass to ground with a 0.1f ceramic capacitor. sdo (pin 46): in serial programming mode, (par/ ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control regis- ters and can be latched on the falling edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v to 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), sdo selects 3.5ma or 1.75ma lvds output currents. when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. v ref (pin 48): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. the reference output is nominally 1.25v. LTC2271 12 2271f sense (pin 50): reference programming pin. connecting sense to v dd selects the internal reference and a 1.05v input range. connecting sense to ground selects the internal reference and a 0.525v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.84 ? v sense . lvds outputs the following pins are differential lvds outputs. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. pin functions out2d C /out2d + , out2c C /out2c + , out2b C /out2b + , out2a C /out2a + (pins 23/24, 25/26, 27/28, 29/30): serial data outputs for channel 2. in 1-lane output mode only out2a C /out2a + are used. in 2-lane output mode only out2a C /out2a + and out2b C /out2b + are used. fr C /fr + (pins 31/32): frame start outputs. dco C /dco + (pins 35/36): data clock outputs. out1d C /out1d + , out1c C /out1c + , out1b C /out1b + , out1a C /out1a + (pins 37/38, 39/40, 41/42, 43/44): serial data outputs for channel 1. in 1-lane output mode only out1a C /out1a + are used. in 2-lane output mode only out1a C /out1a + and out1b C /out1b + are used. functional block diagram diff ref amp ref buf 2.2f 1f 1f 1f 1f refh refl range select 1.25v reference refh refl v cm1 v cm2 v dd /2 sdo 2271 f01 cs s/h sense v ref 2.2f mode control registers sck par/ ser sdi 16-bit adc core ch2 analog input ch1 analog input s/h 16-bit adc core out1a out1b out1c out1d out2a out2b out2c out2d data clock out frame data serializer ognd ov dd enc C v dd enc + 1.8v 1.8v pll figure 1. functional block diagram 13 2271f LTC2271 applications information converter operation the LTC2271 is a low power, 2-channel, 16-bit, 20msps a/d converter that is powered by a single 1.8v supply. the analog inputs must be driven differentially. the encode input can be driven differentially or single ended for lower power consumption. to minimize the number of data lines the digital outputs are serial lvds. each channel outputs one bit at a time (1-lane mode), two bits at a time (2-lane mode) or four bits at a time (4-lane mode). many additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and- hold circuits (figure 2). the inputs should be driven differentially around a common mode voltage set by the v cm1 or v cm2 output pins, which are nominally v dd /2. for the 2.1v input range, the inputs should swing from v cm C 525mv to v cm + 525mv. there should be 180 phase difference between the inputs. c sample 17pf r on 24 r on 24 v dd v dd LTC2271 a in + 2271 f02 c sample 17pf v dd a in C enc C enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 figure 2. equivalent input circuit. only one of two analog channels is shown the two channels are simultaneously sampled by a shared encode circuit (figure 2). input drive circuits input filtering if possible, there should be an rc lowpass ? lter right at the analog inputs. this lowpass ? lter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc ? lter. the rc component values should be chosen based on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its optimal dc level. at higher input frequencies a transmission line balun transformer (figures 4 to 5) has better balance, resulting in lower a/d distortion. LTC2271 14 2271f applications information 25 25 25 25 50 0.1f a in + a in C 12pf 1f v cm LTC2271 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 2271 f03 figure 3. analog input circuit using a transformer. recommended for input frequencies from 1mhz to 40mhz 25 25 50 12 12 0.1f a in + a in C 8.2pf 1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 2271 f04 LTC2271 figure 4. recommended front-end circuit for input frequencies from 5mhz to 80mhz 25 25 50 0.1f a in + a in C 1.8pf 1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 2271 f05 LTC2271 figure 5. recommended front-end circuit for input frequencies above 80mhz 25 25 200 200 0.1f a in + a in C 1f 12pf 12pf v cm LTC2271 2271 f06 C + analog input high speed differential amplifier 0.1f figure 6. front-end circuit using a high speed differential ampli? er figure 7. dc-coupled ampli? er ampli? er circuits figure 6 shows the analog input being driven by a high speed differential ampli? er. the output of the ampli? er is ac coupled to the a/d so the ampli? ers output common mode voltage can be optimally set to minimize distortion. if dc coupling is necessary use a differential ampli? er with an output common mode set by the LTC2271 v cm pin (figure 7). 25 25 a in + a in C 1f 25pf 25pf v cm LTC2271 2271 f07 C C + + analog input cm 15 2271f LTC2271 applications information reference the LTC2271 has an internal 1.25v voltage reference. for a 2.1v input range using the internal reference, connect sense to v dd . for a 1.05v input range using the internal reference, connect sense to ground. for a 2.1v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.68 ? v sense . the v ref , refh and refl pins should be bypassed as shown in figure 8. a low inductance 2.2f interdigitated capacitor is recommended for the bypass between refh and refl. this type of capacitor is available at a low cost from multiple suppliers. alternatively, c1 can be replaced by a standard 2.2f capacitor between refh and refl. the capacitors should be as close to the pins as possible (not on the back side of the circuit board). figure 8c and 8d show the recommended circuit board layout for the refh/refl bypass capacitors. note that in figure 8c, every pin of the interdigitated capacitor (c1) is connected since the pins are not internally connected in some vendors capacitors. in figure 8d the refh and refl pins are connected by short jumpers in an internal layer. to minimize the inductance of these jumpers they can be placed in a small hole in the gnd plane on the second board layer. figure 8a. reference circuit sense 1.25v external reference 2.2f 1f v ref 2271 f09 LTC2271 figure 9. using an external 1.25v reference v ref refh refh sense c1 tie to v dd for 2.1v range; tie to gnd for 1.05v range; 3 " / ( & t 7 sense for 0.625v < v sense < 1.300v 1.25v refl refl internal adc high reference buffer 2271 f08a LTC2271 5 0.84x diff amp internal adc low reference c1: 2.2f low inductance interdigitated capacitor tdk clle1ax7s0g225m murata lla219c70g225m avx w2l14z225m or equivalent 1.25v bandgap reference 0.625v range detect and control 2.2f c2 1f c3 1f + + C C C C + + refh refh refl refl 2271 f08b LTC2271 capacitors are 0402 package size c3 1f c1 2.2f c2 1f figure 8b. alternative refh/refl bypass circuit figure 8c. recommended layout for the refh/refl bypass circuit in figure 8a figure 8d. recommended layout for the refh/refl bypass circuit in figure 8b 2271 f08c 2271 f08d LTC2271 16 2271f encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10), and the single-ended encode mode (figure 11). the differential encode mode is recommended for sinu- soidal, pecl, or lvds encode inputs (figures 12, 13). the encode inputs are internally biased to 1.2v through 10k equivalent resistance. the encode inputs can be taken above v dd (up to 3.6v), and the common mode range is from 1.1v to 1.6v. in the differential encode mode, enc C should stay at least 200mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + should have fast rise and fall times. the single-ended encode mode should be used with cmos encode inputs. to select this mode, enc C is con- nected to ground and enc + is driven with a square wave applications information encode input. enc + can be taken above v dd (up to 3.6v) so 1.8v to 3.3v cmos logic levels can be used. the enc + threshold is 0.9v. for good jitter performance enc + should have fast rise and fall times. if the encode signal is turned off or drops below approximately 500khz, the a/d enters nap mode. figure 12. sinusoidal encode drive enc + enc C pecl or lvds clock 0.1f 0.1f 2271 f13 LTC2271 figure 13. pecl or lvds encode drive 50 100 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 LTC2271 2271 f12 enc C enc + 0.1f v dd LTC2271 2271 f10 enc C enc + 15k v dd differential comparator 30k figure 10. equivalent encode input circuit for differential encode mode 30k enc + enc C 2271 f11 0v 1.8v to 3.3v LTC2271 cmos logic buffer figure 11. equivalent encode input circuit for single-ended encode mode clock pll and duty cycle stabilizer the encode clock is multiplied by an internal phase-locked loop (pll) to generate the serial digital output data. if the encode signal changes frequency or is turned off, the pll requires 25s to lock onto the input clock. a clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. in the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. in the parallel programming mode the duty cycle stabilizer is always enabled. 17 2271f LTC2271 applications information digital outputs the digital outputs of the LTC2271 are serialized lvds signals. each channel outputs one bit at a time (1-lane mode), two bits at a time (2-lane mode) or four bits at a time (4-lane mode). please refer to the timing diagrams for details. in 4-lane mode the clock duty cycle stabilizer must be enabled. the output data should be latched on the rising and falling edges of the data clock out (dco). a data frame output (fr) can be used to determine when the data from a new conversion result begins. the minimum sample rate for all serialization modes is 5msps. by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt- age. an external 100 differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd which is isolated from the a/d core power. table 1. maximum sampling frequency for all serialization modes serialization mode maximum sampling frequency, f s (mhz) dco frequency fr frequency serial data rate 4-lane 20 2 ? f s f s 4 ? f s 2-lane 20 4 ? f s f s 8 ? f s 1-lane 20 8 ? f s f s 16 ? f s programmable lvds output current in lvds mode, the default output driver current is 3.5ma. this current can be adjusted by control register a2 in the serial programming mode. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. in the parallel programming mode the sdo pin can select either 3.5ma or 1.75ma. optional lvds driver internal termination in most cases using just an external 100 termination resistor will give excellent lvds signal integrity. in addi- tion, an optional internal 100 termination resistor can be enabled by serially programming mode control register a2. the internal termination helps absorb any re? ections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. internal termination can only be selected in serial programming mode. data format table 2 shows the relationship between the analog input voltage and the digital data output bits. by default the output data format is offset binary. the 2s complement format can be selected by serially programming mode control register a1. table 2. output codes vs input voltage a in + -a in C (2v range) d15-d0 (offset binary) d15-d0 (2 s complement) >1.000000v +0.999970v +0.999939v 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 1111 0111 1111 1111 1111 0111 1111 1111 1110 +0.000030v +0.000000v C0.000030v C0.000061v 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1110 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 C0.999939v C1.000000v 19 2271f LTC2271 applications information the ? rst bit of the 16-bit input word is the r/ w bit. the next seven bits are the address of the register (a6:a0). the ? nal eight bits are the register data (d7:d0). if the r/ w bit is low, the serial data (d7:d0) will be writ- ten to the register set by the address bits (a6:a0). if the r/ w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin (see the timing diagrams). during a read back command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200 impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, table 4. serial programming mode register map (par/ ser = gnd) register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 resetxxxxxxx bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. this bit is automatically set back to zero at the end of the spi write command. the reset register is write-only. data read back from the reset register will be random. bits 6-0 unused, dont care bits. register a1: format and power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_2 x x nap_1 bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 5 twoscomp twos complement mode control bit 0 = offset binary data format 1 = twos complement data format bits 4, 3, 0 sleep:nap_2:nap_1 sleep/nap mode control bits 000 = normal operation 0x1 = channel 1 in nap mode 01x = channel 2 in nap mode 1xx = sleep mode. both channels are disabled. note: any combination of channels can be placed in nap mode bits 1, 2 unused, dont care bits then sdo can be left ? oating and no pull-up resistor is needed. table 4 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the ? rst serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is automatically set back to zero. LTC2271 20 2271f applications information register a2: output mode register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 ilvds2 ilvds1 ilvds0 termon outoff outtest outmode1 outmode0 bits 7-5 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 4 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2 the current set by ilvds2:ilvds0 bit 3 outoff output disable bit 0 = digital outputs are enabled 1 = digital outputs are disabled bit 2 outtest digital output test pattern control bit 0 = digital output test pattern off 1 = digital output test pattern on bits 1-0 outmode1:outmode0 digital output mode control bits 00 = 2-lane output mode 01 = 4-lane output mode 10 = 1-lane output mode 11 = not used register a3: test pattern msb register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 tp15 tp14 tp13 tp12 tp11 tp10 tp9 tp8 bits 7-0 tp15:tp8 test pattern data bits (msb) tp15:tp8 set the test pattern for data bit 15 (msb) through data bit 8. register a4: test pattern lsb register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 bits 7-0 tp7:tp0 test pattern data bits (lsb) tp7:tp0 set the test pattern for data bit 7 through data bit 0 (lsb). 21 2271f LTC2271 applications information grounding and bypassing the LTC2271 require a printed circuit board with a clean unbroken ground plane. a multilayer board with an in- ternal ground plane in the ? rst layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref , refh and refl pins. bypass capacitors must be located as close to the pins as possible. size 0402 ceramic capacitors are recommended. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. of particular importance is the capacitor between refh and refl. this capacitor should be on the same side of the circuit board as the a/d, and as close to the device as possible. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground ? ll and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the LTC2271 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias. typical applications LTC2271 v cm1 gnd a in1 + a in1 C gnd refh refl refh refl par/ ser a in2 + a in2 C gnd v cm2 out1c + out1c C out1d + out1d C dco + dco C ov dd ognd fr + frC out2a + out2a C out2b + out2b C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 40 39 38 37 36 35 34 33 32 31 30 29 28 27 v dd v dd sense gnd v ref gnd sdo gnd out1a + out1a C out1b + out1b C 52 51 50 49 48 47 46 45 44 43 42 41 15 16 17 18 19 20 21 22 23 24 25 26 v dd v dd enc + enc C cs sck sdi gnd out2d C out2d + out2c C out2c + C + C + C + C + cn1 c3 1f c29 1f c4 2.2f c2 1f c16 0.1f 2271 ta02 ov dd digital outputs c37 1f c7 0.1f c5 0.1f v dd sense sdo v dd encode input spi port par/ ser a in1 + a in1 C a in2 + a in2 C cn1: 2.2f low inductance interdigitated capacitor tdk clle1ax7s0g225m murata lla219c70g225m avx w2l14z225m or equivalent LTC2271 22 2271f typical applications top side inner layer 3 inner layer 5 inner layer 2 inner layer 4 bottom side 23 2271f LTC2271 package description ukg package 52-lead plastic qfn (7mm 8mm) (reference ltc dwg # 05-08-1729 rev ?) 7.00 p 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.30 typ or 0.35 s 45 o c chamfer 0.40 p 0.10 52 51 1 2 bottom viewexposed pad top view side view 6.50 ref (2 sides) 8.00 p 0.10 (2 sides) 5.50 ref (2 sides) 0.75 p 0.05 0.75 p 0.05 r = 0.115 typ r = 0.10 typ 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 6.45 p 0.10 5.41 p 0.10 0.00 C 0.05 (ukg52) qfn rev ? 0306 5.50 ref (2 sides) 5.41 p 0.05 6.45 p 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p 0.05 6.10 p 0.05 7.50 p 0.05 6.50 ref (2 sides) 7.10 p 0.05 8.50 p 0.05 0.25 p 0.05 0.50 bsc package outline LTC2271 24 2271f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 1012 ? printed in usa typical application 16-bit adc core ch1 analog input ch2 analog input encode input s/h 16-bit adc core out1a out1b out1c out1d out2a out2b out2c out2d data clock out frame s/h data serializer pll ognd 2271 ta05 serialized lvds outputs gnd v dd ov dd 1.8v 1.8v integral non-linearity (inl) output code 0 C2.0 C1.5 C1.0 inl error (lsb) C0.5 0.5 0.0 1.0 1.5 2.0 16384 32768 49152 65536 2271 ta06 related parts part number description comments adcs ltc2160 16-bit 25msps, 1.8v adc, ultralow power 45mw, 77db snr, 90db sfdr, ddr lvds/ddr cmos/cmos outputs, 7mm 7mm qfn-48 ltc2180 16-bit 25msps, 1.8v dual adc, ultralow power 39mw/ch, 77db snr, 90db sfdr, ddr lvds/ddr cmos/cmos outputs, 9mm 9mm qfn-64 ltc2188 16-bit 20msps, 1.8v dual adc, ultralow power 38mw/ch, 77db snr, 90db sfdr, ddr lvds/ddr cmos/cmos outputs, 9mm 9mm qfn-64 ltc2190 16-bit 25msps, 1.8v dual adc, ultralow power 52mw/ch, 77db snr, 90db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2202/ltc2203 16-bit 10msps/25msps 3.3v adcs 140mw/220mw, 81.6db snr, 100db sfdr, cmos outputs, 7mm 7mm qfn-48 plls ltc6946-x ultralow noise and spurious integer-n synthesizer with integrated vco 3.7mhz to 5.7ghz, C226dbc/hz normalized in-band phase noise floor, C157dbc/ hz wideband output phase noise floor ltc6945 ultralow noise and spurious 0.35ghz to 6ghz integer-n synthesizer 3.5ghz to 6ghz, C226dbc/hz normalized in-band phase noise floor, C157dbc/hz wideband output phase noise floor signal chain receivers ltm9002 14-bit, dual channel if/baseband module receiver dual adc, dual ampli? ers, anti-alias filters and a dual trim dac in 15mm 11.25mm lga ltm9004 14-bit, direct conversion module receiver i/q demodulator, baseband ampli? ers, lowpass filters up to 20mhz, dual 14-b it 125msps adc in 22mm 15mm lga rf mixers/demodulators ltc5569 300mhz to 4ghz dual active downconverting mixer high iip3: 26.8dbm, 2db conversion gain, low power: 3.3v/600mw, integrated rf transformer for compact footprint ltc5584 30mhz to 1.4ghz wideband i/q demodulator i/q demodulation bandwidth >530mhz, 31dbm iip3, iip2 adjustable to >80dbm, dc offset adjustable to zero, 45db image rejection ltc5585 700mhz to 3ghz wideband i/q demodulator i/q demodulation bandwidth >530mhz, 25.7dbm iip3, iip2 adjustable to >80dbm, dc offset adjustable to zero, 43db image rejection |
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